Recently, research and development of a flat panel display device have been intensively carried out. Examples of the flat panel display device include a liquid crystal display, the EL display, an FED (Field Emission Device) display and the like. Particularly, the liquid crystal display and an organic EL display are noted as a display device for use in a mobile phone, a mobile personal computer and the like, taking advantage of their light weight and low power consumption. On the other hand, as those portable devices are getting equipped with more functions, there is an increasing demand for not only a power-use battery of higher capacity and also a display device of lower power consumption for attaining as long working duration as possible.
Japanese Unexamined Patent Publication No. 194205/1996 (Tokukaihei 8-194205 published on Jul. 30, 1996) is a typical example of prior art, which discloses a method to reduce power consumption of a display device. With this method, in order to perform gray-scale display with low power consumption, each pixel is provided with a memory function; switching a reference voltage, which matches the storage content of the pixel, stops periodical rewriting in the case of displaying an identical image, thereby reducing power consumption of a driving circuit.
More specifically, as shown in FIG. 17, pixel electrodes 1 are arranged in a matrix on a first glass substrate. Between the pixel electrodes 1, scanning lines 2 are disposed in a lateral direction, and signal lines 3 are disposed in a longitudinal direction. Furthermore, reference lines 4 are disposed parallel with the scanning lines 2. In a portion enclosed by the scanning lines 2 and the signal lines 3, a memory element 5 is provided. A switching element 6 is disposed linking the memory element 5 and the pixel electrode 1.
The scanning lines 2 are selectively controlled by a scanning line driver 7 every vertical period, while the signal lines are collectively controlled by a signal line driver 8 every horizontal period. The reference lines 4 are collectively controlled by a reference line driver 9. Above the first glass substrate, a second glass substrate is provided in such a manner that the second glass substrate faces the first glass substrate with a predetermined distance therebetween. The second glass substrate has counter electrodes on a surface that faces the first glass substrate. Further, the first and second glass substrates seal a liquid crystal in between. The liquid crystal, which is an electro-optical element, is used as a display material.
FIG. 18 is a circuit diagram illustrating in detail an arrangement of each pixel portion shown in FIG. 17. In a portion enclosed by the scanning lines 2 and the signal lines 3 that are disposed to intersect at right angles, the memory element 5 for storing binary data is provided. Information stored in the memory element 5 is outputted via the 3-terminal switching element 6 made of a TFT. The switching element 6 has a control input terminal which receives output from the memory element 5. One end of the switching element 6 receives a reference voltage Vref of the reference line 4, and the other end receives a common voltage Vcom of the counter electrode 11 from the pixel electrode 1 via a liquid crystal layer 10 in between. In this manner, a resistance across the switching element 6 is controlled in accordance with output from the memory element 5, thereby adjusting a bias condition of the liquid crystal layer 10.
In the arrangement of FIG. 18, the memory element 5 is provided with two-stage inverters 12, 13, each made of a poly-Si TFT, and a memory circuit subjected to positive feedback, that is, a static memory element. When the scanning line 2 is selected because of High level of its scanning voltage Vg, a TFT 14 is brought into conduction (“ON”, hereinafter), so that a signal voltage Vsig from the signal line 3 is inputted to a gate terminal of the inverter 12 via the TFT 14. The output of the inverter 12 is inverted by the inverter 13, then, inputted again to the gate terminal of the inverter 12. In this manner, data fed to the inverter 12 when the TFT 14 is ON is, with the same polarity, fed back to the inverter 12, and held until the TFT 14 is turned ON again.
Further, another arrangement in which a static memory element is provided in each pixel by using the poly-Si TFT, as with the foregoing arrangement, is disclosed in another prior art document, i.e., Japanese Unexamined Patent Publication No. 148687/1990 (Tokukaihei 2-148687 published on Jun. 7, 1990; JP Patent No. 2729089). FIG. 19 is a circuit diagram showing an arrangement of each pixel portion of the foregoing prior art. According to the prior art, each pixel is controlled by a plurality of memory cells m1, m2 to mn (in FIG. 19, n=4), a constant current circuit 21 and data of the respective memory cells m1 to mn. The pixel includes FETs q1 to qn which produce a reference current of the constant current circuit 21, and an organic EL element 22 which is driven by a current from the constant current circuit 21. The memory cells m1 to mn corresponding to the same pixel share a feed of a row electrode control signal vl, and are respectively fed n-bit column electrode control signals bi to bn.
The constant current circuit 21 is a current mirror circuit using FETs 23, 24. Therefore, a current passing through the organic EL element 22 is determined by the reference current that is the sum total of currents passing through the FETs q1 to qn which are connected parallel to one another. Furthermore, a current passing through the FETs q1 to qn is determined by data stored in the memory cells m1 to mn.
Each of the memory cells m1 to mn is arranged, for example, as shown in FIG. 20. More specifically, each of the memory cells m1 to mn includes an input inverter 25, a storage inverter 26, a feedback inverter 27, and MOS transmission gates 28, 29 for controlling, in response to the row electrode control signal vl and output from the input inverter 25, by determining which to do, inputting the column electrode control signals b1 to bn, or feeding back output from the feedback inverter 27, with respect to the gate of the storage inverter 26. In this manner, the foregoing is a static memory element arrangement such that output from the storage inverter 26 is fed back to the gate of the storage inverter 26 via the feedback inverter 27 and the MOS transmission gate 29.
Further, yet another prior art document is Japanese Unexamined Patent Publication No. 227608/2000 (Tokukai 2000-227608 published on Aug. 15, 2000) which discloses such a circuit configuration of a liquid crystal display device that an image memory is provided outside a display section. FIG. 21 is a block diagram showing a display substrate of the prior art. According to the prior art, a display section 31 is connected to an image memory 33 via a line buffer 32 in between. The image memory 33 shows an arrangement of a random access memory, in which memory cells are aligned in a matrix, and has a bit map arrangement in which address space is the same as that of a pixel of the display section 31.
An address signal 34 is inputted to a memory line selection circuit 36 and a column selection circuit 37 via a memory control circuit 35. A memory cell which was specified by the address signal 34 is selected by a column line and a row line, though not shown, and display data 38 is written into the memory cell thus selected. The display data 38 thus written is then outputted, as a line portion of data including a selection pixel, to the line buffer 32. The line buffer 32 is connected to signal wiring of the display section 31. Therefore, the read-out display data 38 is outputted to the signal wiring, though not shown.
Meanwhile, the address signal 34 is also inputted to an address line conversion circuit 39. Therefore, of all line selection wires of the display section 31, which are not shown, a line selection wire which is obtained by converting the address signal 34 is selected by a display line selection circuit 40, and a selection voltage is applied accordingly. Such operation causes the display data 38 to be fed from the image memory 33 to the display section 31.
FIG. 22 is a circuit diagram showing an example of a circuit configuration of each pixel pertaining to the display section 31. Selection of a line selection wire 41 made by the display line selection circuit 40 causes the following: a control TFT 42 which is connected to the line selection wire 41 is controlled; the display data 38 fed by the line buffer 32 via a signal wire 43 is stored by a capacitor 45 which is provided between a common wire 44 and the control TFT 42; and a terminal voltage of the capacitor 45 controls a driving TFT 46 to be ON or OFF. A determination of a conduction state of the driving TFT 46 being ON or OFF further determines in what manner a voltage from a liquid crystal reference wire 48 is applied to a pixel electrode 47: directly, or indirectly via a capacitor 49 provided between terminals of the driving TFT 46.
Further, FIG. 23 is a circuit diagram showing another example of a circuit configuration of each pixel pertaining to the display section 31. In this configuration, an analog switch 51 is used as a TFT for driving a liquid crystal. The analog switch 51 is made up of a p-type TFT 52 and an n-type TFT 53. In order to drive the analog switch 51, two systems of memory circuits, which respectively include a sampling capacitor 54, 55 and a sampling TFT 56, 57, are provided corresponding to the TFTs 52, 53.
The sampling TFTs 56, 57 are respectively connected to two data wires 58, 59 which have different polarities, while being connected to the same line selection wire 41. The line selection wire 41 controls ON or OFF of the sampling TFTs 56, 57, and voltages D, /D of the data wires 58, 59 are respectively stored in the sampling capacitors 54, 55. Note that, this Publication also discloses that (i) the voltages D, /D which have different polarities and used to drive the analog switch 51 are not stored by providing two systems of memory circuits unlike the foregoing, but are produced by an inverter circuit inside a pixel, and (ii) the memory circuit may be configured on the display section 31 by adopting a configuration of a memory circuit used for a semiconductor, in which a TFT is used.
Thus, the Publication 227608/2000 discloses an arrangement of a polysilicon TFT substrate having the image memory 33 in addition to the display section 31 for a liquid crystal display use.
However, according to prior art disclosed in the Publication 194205/1996, as shown in FIG. 18, one pixel is made up of a liquid crystal layer 10, a liquid crystal driving switching element 6 and a 1-bit memory element 5. This raises a problem that multi-gray-level display of not less than 3 gray-levels cannot be performed, though black and white binary display per liquid crystal element can be performed.
Likewise, even in the prior art disclosed in the Publication 227608/2000, as shown in FIG. 22, one pixel is provided only with a liquid crystal element and a 1-bit memory element made up of the capacitor 45. This raises a problem that not more than black and white binary display per liquid crystal element can be performed.
In this respect, in the prior art of the Publication 148687/1990, as shown in FIG. 19, one pixel is made up of the organic EL element 22, the current mirror circuit 21 and the plurality of memory cells m1 to mn. Therefore, it is possible to realize multi-gray-level display in accordance with the number n of the memory cells by rewriting a condition of the memory cells m1 to mn.
However, the arrangement of FIG. 19 requires the column electrode control signals b1 to bn, corresponding to data wires, the number of which is the same as the number n of the memory cells necessary for the multi-gray-level display. Therefore, as levels of gray are increased in the multi-gray-level display, pixels are covered with more wires. This raises a new problem that an area to create a memory cell and the like narrows.
Further, in the arrangement disclosed in the Publication 227608/2000, a 1-scanning line portion of data is read out of the image memory 33 in parallel, then, transmitted to the line buffer 32. Thus transmitting the data in parallel from the image memory 33 to a buffer circuit (or a signal line driver) has the merit such that it does not require to take the following steps: parallel/serial conversion is performed with respect to a 1-line portion of data, and the data, now serial data, is transferred through the inside of a shift register, not shown, of the signal line driver 8 of FIG. 17, then, the serial/parallel conversion is performed again with respect to the transferred data. This arrangement can realize low power consumption accordingly.
However, in the case where multi-gray-level display of not less than 3 gray-levels per pixel is performed according to this arrangement, it should be arranged such that data which is read out of the image memory 33 is converted to an analog voltage in a D/A converter provided inside the signal line driver 8. This raises a problem that large power consumption is required by D/A conversion.
Furthermore, even in the arrangement of the Publication 148687/1990, the reference current that is produced by the FETs q1 to qn and then passes through the side of the FET 23 of the current mirror circuit 21 becomes unwanted. Regarding the current mirror circuit 21 as a kind of D/A converter, there arises, again, the problem of large power consumption due to D/A conversion.